Tag: RISC-V

Imperas will host the RISC-V panel session with like-minded industry peers and Calista Redmond, CEO of RISC-V International, as moderator ...

ImperasDV processor verification solutions enable 'step-compare' advanced functional verification including asynchronous events, plus verification IP reusability with RVVI Close up ...

The MIPS flexible compute solutions are now supported with Imperas reference models and Ashling SDK tools, ready for the complete ...

ImperasDV™ verification solutions are now certified for use with Synopsys functional simulation and debug tools with 'lock-step-compare' for RISC-V processor ...

Imperas RISC-V reference models, simulator, tests, and verification IP are supporting Ventana Micro in delivering a performance-leading family of data ...

These latest models support the NS family of standard processors in safety-critical and next-generation embedded systems, for developers using Imperas ...

ImperasDV is based on the trusted Imperas reference models and Verification IP, combined with architectural validation test suites and coverage ...

Building on 35 years of innovation in RISC processor development, MIPS' strategic move to RISC-V is supported by Imperas RISC-V ...

Imperas leadership in the RISC-V Verification Ecosystem recognized in the expanded OpenHW Verification Task Group charter to lead the RISC-V ...

Imperas reference models for Andes expanded with Andes Custom Extension™ support and design flow integration for leading EDA environments, plus ...