Power reduction has been on the top priority list of chip designers. The question at hand is: are positioned to address this problem? Are we getting the best combination of power, performance, and area in our chips? Are the EDA tools that we are using equipped to do so? What steps can we take to resolve this challenge? With the advent of personal computers and integrated circuits, the target has been to fit as many transistors as possible in one chip and make them run at the highest possible frequency. A lot of effort has gone in meeting computing scale and performance requirements, from personal computers to data servers, essentially sidelining power optimization or reduction in holistic ways – although it has been constantly considered in implementation flows.
For the last couple of years, the demand for portable devices has increased rapidly; as a result, the semiconductor industry needs to be limit power consumption of chips. The chip design industry is driven towards low power development due to the widespread use of devices, which require minimal power consumption and maximum speed, such as 4G/5G smartphones, healthcare devices that generate data continuously, smart wearables, and other edge computing devices.
Hence, developing varied and multiple real-time functionalities in these devices requires the design of millions of gate counts on a single chip. Also, the speed is another major consideration in such designs. To meet all these demands, chip design with low power transistors like FinFET has been adopted rapidly.
In order to sustain the ecosystem of always-connected personal/portable devices – which have similar computing capacity and power optimization requirements –the demand for low power has increased in the semiconductor domain. Although servers and network SoCs are not dependent on battery power, overall power footprint and heat dissipation pose major challenges in terms of maintenance, cost and scale.
Here is the formula for dynamic power:
Power = F Cload Vdd2
F – Operating frequency means the speed of digital design.
Cload – capacitance. We can say ‘bigger the chip, bigger the capacitance.’
Vdd2 – supply voltage of the chip
Key causes of power dissipation
- Shrinking transistors have always underscored theoretical predictions in terms of power, more so because transistors or gates no longer dominate power consumption in chips. Leakage power also increases as feature size decreases.
- Interconnect metal wire width. As the metal width shrinks it leads to the consumption of more switching power.
- Faster processing speeds. This causes more switching and hence more power consumption occurs in charging and discharging.
- High die temperature is one of the reasons for higher power consumption. It reduces the battery life.
Chip designers trade-off between performance, power, and area (PPA), prioritizing one over the other to meet the spec. For a long time, it has been performance first and then the area; power optimization has been left for implementation techniques to optimize. Reducing usage of low VT gates (high leakage), smart clock gating insertion, and vector-based dynamic power reduction are a few techniques in implementation, with zero or minimal changes to design.
Usage of UPF/CPF – power formats that allow certain parts of the design to be dynamically switched off during non-operation – are more advanced techniques which require the involvement of a number of team members, from architects to implementation engineers. This is one step closer to where designs are built with power in mind first, while performance and area are taken into consideration after that.
Moore’s law still holds true to a great extent after 50 years, only that number of transistors doubling in the same area is taking slightly longer than 2 years. This is partly because of the new challenges posed by complex technology nodes as well as holistic power reduction techniques.
We can’t further reduce power consumption with technology nodes, “One of the big limiting factors is that a designer, especially a digital designer, has a very good intuitive feel for performance and for area impact, silicon impact, but the gut instinct isn’t exactly there for power,” Pursley says.
The supply voltage of chips is continuously reduced with lower technology node in order to reduce power consumption. As a result, there are very low noise and variation margins. At the same time, the IR drop is increased due to higher interconnect resistance. Due to the IR drop, chip temperature increases and it affects reliability the most.
Low-power design flows need to specify the desired power architecture to be used at each major step of design implementation flow. Traditional implementation flows have failed to address the additional considerations for incorporating advanced low-power techniques. Consequently, designers often resorted to methodologies that were not very user friendly and flexible.
These methodologies required the designer to manually model the impact of low-power during simulation, and provide multiple definitions for the same information: one set for technology synthesis, one for arranging logic gates, one for verifying the functionality of design, one for checking physical connectivity, one for IR drop and yet another one for equivalency checking.
Yet after all that manual work, there was no guarantee of any consistency. Due to this, the risk is increased for manufacturing chips. Manual work increases the chip design cycle time and hence the time to market is increased for the product. Also, designers were unsure about what they made in theory and what was implemented practically. This led to an overall negative impact on the quality of results. In order to help designers to adopt advanced power reduction techniques, a standard power format is developed.
Hence, with improved quality of silicon through easy-to-use “what-if” exploration early in the flow, designers can identify the optimal power architecture to achieve the desired specifications. EDA (Electronic Design Automation) companies have started making tool algorithm in a way that helps in optimizing the design for the three required parameters concurrently.
In addition, by reducing the number of iterations within the flow and limiting silicon re-spins, design teams can predictably address time-to-market concerns. Also, designers have made low power implantation semi-custom by making low-power modules ready to use. Very effective and robust methodologies were developed for verifying these modules as well as the entire design, so that the risk and chip design cycle time has been reduced significantly.
So have we hit the limit in low-power consumption yet? In the words of Torsten Reich, group manager for integrated sensor electronics at Fraunhofer Institute of Integrated Circuits: “Certainly not. R&D will find ways to step further.”
In conclusion, there have been considerable changes as PPA tradeoff has evolved over time. Designers have realized the need of the hour and have accepted new ways of design, starting at architecture. This has been supported by the development of corresponding power standards and EDA tools which incorporates power requirements throughout the design and signoff flow.
