Provides building blocks for RISC-V processor DV with free simulator, architectural validation test suites and SystemVerilog components for evolving Verification Ecosystem
Oxford, United Kingdom, December 9th, 2020 — Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced significant enhancements to its RISC-V processor hardware design verification solutions. This release includes enhanced reference model with SystemVerilog encapsulation / integration and new test bench blocks, new riscvOVPsimPlus™ free simulator, and a range of Imperas developed RISC-V architectural validation tests for the ratified and soon to be ratified RISC-V ISA extensions.
The Free riscvOVPsimPlus RISC-V reference model and simulator, which has been widely adopted across the RISC-V verification ecosystem, has been updated and extended with additional features including full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options. Additionally, included in the updated model are the full standard CLIC features, Debug Module / Mode, “H” Hypervisor simulation, and also ‘near-ratified’ ISA extensions for Vector “V”, Bit Manipulation “B”, and Crypto (Scalar) “K” extensions.
To support the SystemVerilog encapsulation of the reference model, the Imperas RISC-V Processor Verification IP (VIP) package includes example SystemVerilog supporting components and modules for interfacing and synchronization between the Imperas RISC-V golden reference model and the RTL core under test in a step-and-compare verification flow. This approach covers the important aspects of asynchronous events and debug mode operation while also supporting the DV engineer’s active investigation directly at the point of interest during test failure analysis and resolution.
Coverage is a key aspect for any verification plan, as it helps measure the progress toward the quality targets for design completion and tape-out milestones. To support instructional and architectural functional coverage the Imperas RISC-V golden reference model has been further enhanced with built-in monitors to provide coverage metrics without the need for post-simulation processing or other delays with log file analysis.
To help developers ensure their processor design meet the RISC-V specifications, Imperas has developed a directed test instruction generator and is now making many architectural validation test suites available. Suites totaling over 3.5 million instructions now available include:
-Test suites for RV32/64IMC ratified specifications
-Test suite for RISC-V Vectors
Configured: spec:0.8, xlen:32, elen:32, vlen:256, slen:256, FP:IEEE654
Contact Imperas for spec version 0.9, 1.0 draft and other configs of xlen, elen, vlen, slen
-Test suite for RISC-V Crypto 0.8.0 draft specification
-Test suite for RISC-V Bit Manipulation 0.93 draft specification
Imperas provides Extendable Platform Kits (EPK) that are provided as source and include platform, models, scripts, and software to shorten the time to productivity. EPKs include:
-Example platform for use with Google RISCV-DV Instruction Stream Generator flow
-Example platform for step-and-compare SystemVerilog* encapsulation test bench
-Example platform for RISC-V functional coverage
SystemVerilog supported platforms are available for use with our partners Cadence Xcelium , Mentor Questa, Synopsys VCS environments and Metrics cloud-based solutions.
“The open standard ISA of RISC-V is enabling system designers to explore new innovations with optimized processors, which in turn is driving all SoC adopters to expand the design verification plans to cover the specialist processor DV tasks,” said Simon Davidmann, CEO at Imperas Software Ltd. “We are proud of the success the Imperas RISC-V golden reference model has achieved and see the new Verification IP and test suites as a way to help all SoC teams address the challenges of processor DV through the adoption of SystemVerilog test benches with step-and-compare methodologies for processor DV.”
Availability
The free riscvOVPsimPlus package including the test suites and functional coverage analysis are now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus. The riscvOVPsimPlus solution is an entry ramp for development and verification and includes a proprietary freeware license from Imperas, which covers free commercial use as well as academic use. The simulator package also includes a complete open-source model licensed under the Apache 2.0 license.
The RISC-V processor Verification IP, example test benches and any customer specific test suites are Imperas commercial solutions. Imperas also provides solutions for developers of more advanced RISC-V designs, who need multi-core, or custom instruction support and advanced verification techniques.
Imperas also offers a rich library of models for virtual platforms as used in early software development and hardware verification, including methodologies around continuous integration and regression using ‘virtual’ test farms, plus support for hybrid verification platforms with hardware emulators provided by Cadence Palladium, Mentor Veloce, Synopsys Zebu. Further details are available at www.imperas.com/riscv.
RISC-V Summit 2020
Imperas will present technical talks, a tutorial and host a keynote panel on verification at the 2020 RISC V Summit event (December 8-10), including a virtual booth. To meet the Imperas team for demos and discussions, see more details on the free keynotes, exhibits and a special discount code for the full conference go to link:
https://www.imperas.com/articles/imperas-3rd-annual-risc-v-summit-december-8-10-2020